The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). The FinFET gets its name from the fin-like structure which extends from a substrate on which it is formed, and which is used to form the FET channel. FinFETs are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes and their three-dimensional structure allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. In addition, high-permittivity (high-K) dielectric materials have been introduced in an effort to reduce gate oxide leakage current while maintaining a desired gate capacitance value. However, high-K dielectrics may suffer from high densities of interfacial and bulk defects, which could increase carrier scattering, degrade mobility, and reduce drain current. At least some efforts to reduce defect densities have included the incorporation of fluorine, for example, which has been shown to effectively passivate interfacial dangling bonds and bulk oxygen vacancies, which in turn may reduce oxide leakage current, improve threshold voltage stability, and generally improve device performance. For the fabrication of planar devices, fluorine incorporation may be achieved by an ion implantation process. However, attempts at fluorine incorporation into FinFET devices by ion implantation may damage the FinFET fins and may be ineffective to introduce fluorine uniformly across the entire three-dimensional geometry of the FinFET fins. Thus, existing techniques have not proved entirely satisfactory in all respects.